Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as the central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data may be transferred between expansion elements such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices and the system devices communicate with and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus masters which can control operations occurring on the computer bus.
Personal computer systems typically are architected in a single bus or dual bus configuration. In a dual bus system, bus masters may operate simultaneously on both buses. In a single bus configuration, however, only one bus master may control the system bus at a given instant in time, because simultaneous activity on the bus is prohibited. Accordingly, efficient use of the system bus by both system devices and I/O devices is an important consideration in the overall system design.
During normal operation of a single bus computer system, both the CPU and the various I/O devices capable of operating as bus masters compete for control of the single system bus. Typically, direct memory access DMA channels handle arbitration between the CPU and the various I/O devices. Once a bus master obtains control of the bus, however, there are no rules to limit the time during which it can maintain exclusive control of the bus. Thus, the system processor could be locked out if a particular I/O device gains control of the bus and maintains such control while performing a time consuming operation, or passes control of the bus to another bus master device. The problem is exaggerated if more than one I/O device having bus master capabilities is installed in the system. In such a case, the multiple I/O devices may alternatively pass control of the system bus back and forth to each other, thereby effectively cutting off the ability of the CPU to access the system bus.
It is an object of the present invention, then, to provide a synchronization and arbitration scheme which determines the ability of a system device or an I/O device to gain access to the system bus, which prevents CPU lockout during normal operation of the computer system, and which permits efficient and effective data transfer over the system bus.